This invention relates to a semiconductor integrated circuit provided with Emitter Coupled Logic (hereinafter referred to as ECL) input/output buffers, and more particularly to a semiconductor integrated circuit provided with ECL input/output buffers capable of reducing power consumption.
Generally, in the case of inputting an input signal of the ECL level from the external to the device such as SRAM or CPU, etc., and outputting an output signal of the ECL level from the above-mentioned device to the external, an ECL input buffer and an ECL output buffer are used, respectively.
Such ECL input buffer and ECL output buffer are shown in FIGS. 1 and 2, respectively. The ECL input buffer shown in FIG. 1 serves to convert an input signal of the ECL level to an output signal of the CMOS level. This ECL input buffer comprises a CMOS circuit comprised of diodes 3a and 3b, a resistor 3c, transistors 4a, 4b, 4c, 5a, 5b and 5c, a transistor 6a, resistors 6b and 6c, and transistors 7a and 7b, and a CMOS circuit comprised of transistors 8a and 8b, and is driven by a first power supply (e.g., power supply of 0 volts) connected to the terminal 1, and a second power supply (e.g., power supply of -5.0 volts) connected to the terminal 2.
On the other hand, the ECL output buffer shown in FIG. 2 serves to convert an input signal of the CMOS level to an output signal of the ECL level. This ECL output buffer comprises transistors 13a, 13b and 13d, resistors 13c and 15a, transistors 14a, 14b, 15b and 16a, a resistor 16b, and diodes 17a and 17b, and is driven by a first power supply connected to the terminal 11 and a second power supply connected to the terminal 12. In addition to the input/output buffer of the above-mentioned type, there is a known ECL input/output buffer of the type that receives an input signal of the ECL level to output an output signal of the ECL level. Further, there is also known an ECL input/output buffer of the type driven by m (.gtoreq.2) number of power supplies.
A conventional semiconductor integrated circuit including such an ECL input/output buffer is shown in FIG. 3. This semiconductor integrated circuit is provided on a Large Scale Integrated circuit (LSI) chip 20. This semiconductor integrated circuit comprises ECL input buffers 21.sub.1, 21.sub.n used when the circuit is in an ordinary operating state after assembly into the system, ECL output buffers 22.sub.1, ... 22.sub.n is used when the circuit is similarly in the ordinary operating state after assembled into the system, test ECL input buffer 23.sub.1, ... 23.sub.n used only when the circuit is assembled into the system and is subject to testing, and test ECL output buffers 24.sub.l, ... 24.sub.n are used only when the circuit is assembled into the system and is similarly subject to testing. In operation, the input buffer 21i (i-1, ...n) is driven by a first power supply voltage delivered through a power supply pad 25a and a second power supply voltage delivered through a power supply pad 25b to apply level conversion or waveform shaping to an input signal of the ECL level inputted through a pad 26i (i=1, ...n) when the circuit is in an ordinary operating state after being assembled to send it to an device (e.g., CPU, etc.) 27 provided at the core section. Further, the output buffer 22.sub.i (i=1, ... n) is driven by a first power supply voltage delivered through a power supply pad 28a and a second power supply voltage delivered through a power supply pad 28b to apply level conversion to a signal sent from the device when the circuit is in the operating state after assembly to provide an output signal of the ECL level to output it to the external through a power supply pad 29.sub.i.
On the other hand, the test input buffer 23.sub.i (i=1, ... n) is driven by a first power supply voltage delivered through a power supply pad 30a and a second power supply voltage delivered through a power supply pad 30b to apply level conversion or waveform shaping to an input signal of the ECL level inputted through a power supply pad 31.sub.i (i=1, ... n) to send it to the device 27. Further, a test output buffer 24.sub.i (i=1, ... n) is driven by a first power supply voltage delivered through a power supply pad 32a and a second power supply voltage delivered through a power supply pad 32b to apply level conversion to a signal outputted from the device 27 when the circuit is subject to test to provide an output signal of the ECL level to output it to the external through a power supply pad 33.sub.i (i-1, ...n). Respective terminals to which the first power supply voltages are applied of the input buffers 21.sub.l, ... 21.sub.n, the output buffers 22.sub.l, ... 22.sub.n, the test input buffers 23.sub.l, ... 23.sub.n, and the test output buffers 24.sub.l, ... 24.sub.n are connected commonly to a power supply line 34a, and respective terminals to which the second power supply voltages are applied of the above mentioned buffers are connected commonly to a power supply line 34b.
As seen from FIGS. 1 and 2, the ECL input/output buffer is of a structure in which a current flows therein as long as any drive voltage is applied thereto. Accordingly, in the conventional semiconductor integrated circuit provided with the test ECL input/output buffers, there was the problem that even after such a semiconductor integrated circuit is assembled into the system, current flows in the test ECL input/output buffers, so power is uselessly consumed.